(1) Field of the Invention
The present invention relates to a method of fabricating integrated circuits on semiconductor substrates, and more particularly to a method for making buried metal plug contacts that interconnect polysilicon layers to device contacts and concurrently making metal plug contacts between the metal wiring and devices on semiconductor substrates.
(2) Description of the Prior Art
Advances in semiconductor process technologies have significantly reduced device size and increased the device packing density on semiconductor substrates. This has resulted in features sizes less than 0.5 micrometers, and aspect ratios (height to width) for contact openings and for spacings between conducting lines that exceed values greater than 1.0. This rough surface topography makes it difficult to form reliable self-aligned contact to devices contact areas on the substrate and also to form reliable electrical interconnections.
To better understand the problem, schematic cross sectional views are shown in FIGS. 1 through 4 for making a conventional prior art self-aligned contacts to a source/drain areas of a field effect transistors (FETs), as are commonly used on static random access memory (SRAM) and dynamic random access memory (DRAM) chips and the likes. Only a portion of the integrated circuit is shown in the Figs. to simplify the discussion. The process is described for forming a self-aligned contact to a common source/drain area between two FETs.
Starting with FIG. 1, the process begins by providing a semiconductor substrate 10 with device areas on which is formed a thin gate 12. Not shown in the Figs, to simplify the drawing, is a thicker field oxide areas that surrounds and electrically isolates the device areas. The field oxide areas are formed, for example, using the Local Oxidation of Silicon (LOCOS) method. A doped first polysilicon layer 18 having a cap oxide layer 20 on the surface is deposited and patterned by conventional photolithographic means and anisotropic plasma etching to form gate electrodes 18 in the device areas and electrically conducting lines elsewhere on the field oxide areas. Also shown in FIG. 1, lightly doped source/drain areas 16 are usually formed in the substrate 10 adjacent to the gate electrodes 18 by ion implantation. A conformal insulating layer 22, such as a silicon oxide, is then deposited on the substrate and etched back to form sidewall spacer 22 on the sides of the gate electrodes, as shown in FIG. 2. A second ion implantation is then used to form a higher dopant concentration in the substrate adjacent to the sidewalls 22 forming the source/drain contacts 16 and 16'.
Now as shown in FIG. 3, a first insulating layer 24, such as a silicon oxide, is deposited on the cap oxide 20/gate electrodes 18 structures and also over the source/drain areas 16 and 16' of the FETs. Self-aligned contact openings are etched in layer 24 to the source/drain areas of the FETs using a conventional photoresist mask and anisotropic etching. One such contact opening 4 is shown in FIG. 3 exposing the source/drain area 16'. The opening 4 also extends over the gate electrodes 18 and is etched down to the cap oxide layer 20. Unfortunately, when the contact opening 4 is etched, it is necessary to over-etch to insure that the surface of the source/drain areas are exposed in the multitude of openings that are formed on semiconductor substrate, such as in the many cell areas on DRAM and SRAM devices. Because of variations in the thickness of layer 24 across the substrate (nonuniform), the non selectivity of the etching to layer 20, and the difficulty in controlling the over-etch, it is difficult to reliably form the self-aligned contacts without exposing the gate electrode 18 and causing shorts, for example, as might occur in regions labeled A in FIG. 3. Although not depicted in the Figs, the problem of over-etching is further complicated when the spacing between the electrodes 18 is less than twice the thickness of the conformal layer 24, since the layer 24 then partially fills in the high aspect ratio spacing forming a more planar surface. This results in a thicker oxide layer 24 in the source/drain area 16', and it becomes necessary to further increase the over etch in layer 24 to form the contact opening 4, and shorts are even more likely to occur.
Continuing with the process, as shown in FIG. 4, a conductivity doped second polysilicon layer 26 or alternatively a polycide layer (a polysilicon layer having a metal silicide on its surface) is deposited and patterned to form the next level of interconnecting metallurgy. However, because of the severe topography in the underlying self-aligned contact opening, it is difficult to deposit layer 30 with good step coverage. Furthermore, it is difficult to pattern layer 26 using anisotropic etching without leaving residue from layer 26 on the sidewall between the closely spaced polysilicon lines, which can result in intralevel shorts.
The FET structures having these conventionally formed self-aligned contact are then completed to the first level metal interconnects, as shown in FIG. 5. A planar insulating layer 30, composed, for example, of borophosphosilicate glass (BPSG) is deposited over the patterned second polysilicon layer 26. Contact openings are etched, for example, in the peripheral areas of the chip to contact the polysilicon layers and to contact the substrate surface. The contact openings are then filled with a metal barrier plug 50, such as by chemical vapor deposition (CVD) using a tungsten hexafluoride (WF.sub.6) gas. A first metal layer 40 is then patterned to complete the integrated circuit up to the first level of metal wiring.
Although metal plugs have been proposed and used extensively for making contacts to the substrate and to the inter polysilicon layers they do not address the problem of making improved self-aligned contacts to the source/drain areas of FETs. For example, T. Hasegawa, U.S. Pat. No. 5,374,591 describes a method of forming tungsten buried plugs in an opening in an insulator to the surface of the substrate that do not have voids, while F. Liou, U.S. Pat. No. 5,371,041 teaches a method of making contact openings with sidewall spaces that taper the sidewall and thereby fills the contact opening with an electrically conductive material that is also void free. Still another invention by J. Cleeves, U.S. Pat. No. 5,366,929 describes a method for forming a metal plug using a seed layer on the contact opening sidewall and selectively growing a conducting material thereon.
However, there is still a strong need in the semiconductor industry for forming device structures having interconnecting metallurgies that conserve processing steps, reduce the rough surface topography over the semiconductor device and provides a metal plug technology that improves the electrical contact between the inter-polysilicon layers and the source/drain contacts.